The design flow for application specific integrated circuits (ASICs) requires that a representation of a ASIC design, typically a netlist that describes connectivity and primitive cell instances, be simulated functionally and for timing values. This simulation is usually accomplished by using a digital simulator prior to manufacturing the physical ASIC. A digital simulator is capable of simulating any timing values that a designer of the ASIC may wish to exercise on the ASIC model via a "testbench." A testbench is a set of stimuli applied to the inputs of the ASIC model. The expected data from these stimuli are strobed from the outputs of the ASIC model during, simulation in the digital simulator.
Whereas the digital simulator is capable of simulating any timing values, automated test equipment (ATE), which is used later to test the actual physical ASIC, have very strict restrictions on what types of timing values are allowable. Since the test patterns used on the ATE are based primarily upon the digital simulations, a method is needed for ensuring that the digital simulations intended for use on the ATE are compatible with these restrictions. One of the most complex tasks in analyzing for ATE compatibility is determining the direction of bi-directional pads at any point in time (i.e. as an output when the ASIC device is driving or when neither the device nor the external components (ATE or tester) is driving, or as an input when the tester is driving data onto the pad).
All ASIC vendors require some kind of extraction of simulation data to create test patterns and all ASIC vendors must ensure tester (ATE) compatibility. As ASIC designs become more complex, and testbenches represent the system more accurately, these vendors will need to adopt methodologies to aid their designers in quick conversion of simulations to test patterns.
A previous model is disclosed in copending patent application Ser. No. 08/299,395, incorporated herein by reference. Previous methods have the following disadvantages: require more complex digital models of all bi-directional pads; more complex testing methods for each model of the bi-directional pads; are typically a non-industry standard methodology; cause multiple iterations of simulation for designers using a design kit; and create an overall more complex design flow by forcing designers to maintain multiple databases for different industry standard third party tools.
The present invention solves the problem of how to provide enough information to any set of tools which could be written to analyze bi-directional pin data for ATE test pattern extraction from digital simulation.